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L50-501 LSI SVM5 Implementation Engineer

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Killexams.com L50-501 Dumps and Real Questions 2019

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L50-501 exam Dumps Source : LSI SVM5 Implementation Engineer

Test Code : L50-501
Test Name : LSI SVM5 Implementation Engineer
Vendor Name : LSI
Q&A : 119 Real Questions

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LSI LSI SVM5 Implementation Engineer

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NFPA 110: ordinary for Emergency and Standby energy systems prolonged Q&A | killexams.com Real Questions and Pass4sure dumps

contemporary Consulting-Specifying Engineer webcast presenters Tom Divine, PE, project supervisor, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs Engineering, reply reader questions on what new code necessities will suggest for consulting engineers.

Tom Divine, PE, Project Manager, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs EngineeringQ: When is it required to have a 3 pole and four pole ATS?

  • Tom Divine: When the generator is a one after the other-derived device, a 4-pole ATS is required for circuits with a neutral.  If the circuit has no neutral, a three-pole ATS will suffice.  The goal of the requirement is to avoid multiple connections between neutral and ground, which may deliver alternate paths for neutral latest, and cause wrong operation of ground fault protection for gadget.
  • Q: With recognize to breaker coordination; what are the favorite electronic trips: LI, LS/I, LSI, or LSIG?

  • Kenneth Kutsmeda: LSI or LSIG are favorite as a result of they provide essentially the most flexibility when trying to coordinate.  in case you try to serve Article seven hundred- or Article 708-class loads, pay cautious attention to the selective coordination requirement when determining go back and forth instruments.
  • Q: Do you advocate dual hot-standby manage PLCs when installing parallel gensets?

  • Kutsmeda: yes, if the undertaking can have the funds for the further cost, i'd recommend twin control PLCs.  This prevents the PLC from fitting a single element of failure.
  • Q: Are schools regarded to be stage 1 or degree 2 amenities? usually, stage 1 is needed for fitness care or mission critical facilities handiest.

  • Divine: “degree 1” describes a equipment whose failure might result in loss of life or severe injury to a person.  That could follow to a mission essential facility, or may not.  It actually applies to any facility that gives vital care.  Intuitively, I’d predict a faculty to be a degree 2 facility, since it doesn’t provide services whose sudden failure would depart someone exposed to injury.  I’d suggest getting the opinion of all the AHJ’s before proceeding with a design, although.  It’s now not inconceivable to make a case that the failure of an emergency gadget all the way through an evacuation event could be catastrophic, and an AHJ could take the view that it’s stage 1.
  • Q: what's the intent/aim of bodily isolating the important department and lifestyles defense branches? Can one have a dangerous impact on the different?

  • Kutsmeda: The separation is mostly to offer protection to against damage and/or a cable fireplace. You do not desire a cable fire on a widely wide-spread circuit taking out a critical circuit.
  • Q: Is mineral-insulated (MI) cable obligatory for not obligatory standby generator feeder circuits?

  • Divine: MI cable isn’t required with the aid of the NFPA codes.  It’s probably the most methods of complying with requirements for fireplace ranking of emergency feeders in NEC 700.9.  It’s my figuring out that some jurisdictions require it for certain functions, however that requirement doesn’t come up from NFPA ninety nine or NFPA 110, or from the NEC.
  • Q: Does the ten-2nd vigour restoration start time apply to the main service or to the conclusion use gadget?

  • Kutsmeda: The NEC states the latest deliver to emergency lights and power shall be attainable with time required for the application but now not to exceed 10 seconds.  In my adventure the AHJ has interpreted that to suggest energy/existing available at the end use equipment.
  • Q: Does the emergency device consist of conductors and different device upstream from an ATS on the regular aspect of the ATS?

  • Kutsmeda: No, the emergency system doesn't include machine or feeders upstream from the ATS on the ordinary aspect.
  • Q: should the emergency provider switchboard that feeds the ATSs be in a separate room from the room that contains the ATSs?

  • Divine: It doesn’t need to be.  NFPA 110 requires that the EPS, which might consist of generators and paralleling gear, to be put in in a separate room for level-1 techniques.  nevertheless it peculiarly allows for EPSS device and transfer switches, to be installed in that room.
  • Q: If the only vital concern is egress lights, can that be addressed with battery lights, and if so, can my system be standby best?

  • Kutsmeda: yes, the equipment can be standby rated if the lights is addressed by means of individual batteries or a primary inverter equipment.  here's quite typical with paralleled systems that may’t meet the 10 2d requirement.
  • Q: When referring to the NEC as regarding the EPSS, do you deserve to additionally agree with article 695 elevators and 517 hospitals for further requirements?

  • Kutsmeda: sure, there are specific necessities in each of those sections for EPSS-classification systems.
  • Q: How lengthy does the crank examine should be accomplished on the generator?

  • Divine: That requirement seems in 7.13.4.four.2 in both the 2010 and 2013 variations of NFPA 110.  They reference the crank and rest cycles described in 5.6.four.2, which calls for 15 seconds of cranking, adopted through 15 seconds of rest, repeated three times.
  • Q: Is the use of closed transition transfer switches informed for level 1 facilities? Any concerns with the usage of closed transition switches?

  • Kutsmeda: Closed transition isn't a requirement.  it is recommended for those methods that don't need to take yet another outage transferring returned to utility.  for example, vigour methods that serve life help or surgical procedure class gadget may additionally wish to accept as true with closed transition.  Many mission critical type facilities use closed transition to prevent the mechanical systems from shutting down all the way through the switch again to utility (vigor backup through UPS).  Closed transition switches deserve to have some class of synch check to steer clear of closing two sources out of part and protection to prevent again-feeding the utility.
  • Q: What are the requirements for the life security and significant branch programs when the constructing—specifically a talented nursing facility—has a full building backup generator? Do you still require separate ATSs, besides the fact that we have separate panels and wiring within the constructing? Contractors consider here's now not essential.

  • Divine: Articles 517.40 through 517.forty four describe necessities for “nursing homes and restricted care amenities.”  Article 517.forty one(B) requires a separate transfer change for every department, unless the whole load is under one hundred fifty kVA.  There’s no exception for a full building backup, and there are requirements for load to be staged onto the equipment.
  • Q: If I even have a device per Article 701 and Article 702 software, what branches do the battery charger, gasoline pump, and dampers get connected to?

  • Kutsmeda: Article 701.  The device required to function the generator will be connected to the highest level for which that generator serves.
  • Q: If a sanatorium is to be 100% backed up with the aid of turbines, is it a violation of NEC 517.30(B)(4)-switch Switches to get rid of all switch switches by using providing Medium Voltage generators and tie them thru a paralleling equipment to a Medium Voltage Distribution Switchgear at the significant Utility Plant? switch of vigour may be at the Medium Voltage switchgear.

  • Divine: Presuming a load of more than 150 kVA, this scheme doesn’t meet the black-letter requirements of 517.30(B)(four), which requires separate switch switches for the emergency branches and the equipment gadget.  I don’t see that the rest in the gadget can organize for delayed connection of the machine gadget, as required in 517.34.  at last, this scheme will run afoul of NFPA 110 6.1.6, 2013 version, which requires transfer switches to be listed assemblies where accessible, and makes it possible for medium-voltage transfer by the use of interlocked circuit breakers for less than mechanical and crucial plant hundreds. 
  • Q: might the 517.34 equipment be considered as a 701 device?

  • Kutsmeda: sure, the hundreds recognized in Article 517.34 part (A) may be considered as a 701 device.  masses identified in 517.34 section (B) could be considered as a 702 system as a result of they are not required to be automatic.
  • Q: To verify under on-website or transportable load financial institution, do amenities have a checking out switch change to connect the weight financial institution to the gadget and supply that auto removal of load financial institution if utility energy fails right through load financial institution testing?

  • Divine: I’ve not ever considered that implementation.  The basic feature of a switch swap is to maintain load energized.  There’s nothing particular about a transfer switch as a method of de-energizing whatever thing like a load bank.  customarily, I’ve considered a committed breaker within the generator distribution switchgear for that purpose, or every so often an outside disconnect change connected to any such breaker.  The requirement is that equal masses—the burden financial institution—get replaced with emergency masses—the power’s load—if the basic supply fails.  That could be carried out with a control relay that journeys the load bank if typical vigor fails, or it might be done through connecting the emergency load as a part of the examine, and supplementing with a load bank.
  • Q: are you able to combine Article seven hundred-class masses and Article 701-classification loads in the equal switchgear and on the identical OCPD of a generator?

  • Kutsmeda: which you can combine seven hundred and 701 class masses on the same switchgear with a standard OCPD on the output of the generator.  The seven hundred and 701 loads should be on separate feeders with separate OCPD on each feeder and the OCPD for the seven-hundred type hundreds need to be determined in separate vertical sections of the switchgear.
  • Q: whereas performing the two hour load verify per 7.13.four.3, I assume the generator OEM manufacturing facility can perform only a 2 hour reactive load verify at rated power factor to agree to 7.13.4.three.2, relevant?

  • Divine: NFPA 7.13.four.3.2 says that the acceptance verify will also be carried out at harmony energy aspect the use of a strictly resistive load financial institution if the manufacturer has tested the mills at rated load and rated vigour ingredient.  
  • – Edited by using Jessica DuBois-Maahs, affiliate content supervisor, CFE Media, jdmaahs(a)cfemedia.com.

    need this text on your web site? click here to sign up for a free account in ContentStream® and make that turn up.


    A Design Methodology for constructing method-unbiased Hardmacro IP | killexams.com Real Questions and Pass4sure dumps

    swiftly migrating highbrow property (IP) from one foundry to yet another and from one technique node to the next will also be a difficult, however indispensable, a part of the business, mainly if the IP is generated and delivered as hardmacro IP.  That’s as a result of tough IP or a GDSII netlist versus soft IP, RTL or gate-stage netlist ought to be accessible for all primary foundries and for a large choice of technique nodes at each foundry.

    Designing new memory IP is essentially a manual assignment that includes greater analog circuits —cost pumps, voltage regulators and experience amplifiers, for example — than most common sense designs.  At four megabytes (Mb), the design burden dealing with the layout supervisor and his implementation crew is bold. 

    These considerations are normal of reminiscence design, and the Kilopass team ran into them when designing a contemporary 4-Mb reminiscence IP block.  Its experience offers techniques through which other groups can overcome these challenges.

    To ease the burden, the group recognized facets of the design that could be automated, liberating them to pay attention to essential analog elements that ought to be tailor-made for someone foundry and technique.  The outcome is an electronic design automation (EDA) device move developed for the newest anti-fuse non-unstable reminiscence (NVM) product line. 

    Exploiting the EDA device circulation

    the use of commercially purchasable EDA solutions, the primary task to be automated was speedy and accurate entry of design concepts, together with managing design intent in a method that flowed naturally in the schematic.  This allowed designers to visualize and take into account the numerous interdependencies of an analog or mixed-signal design and its results on circuit performance.

    In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by using an additional inside team.  The project of merging the current layout with the rest of the memory design became a simple method requiring a day of manual vicinity and route or connecting I/Os and routing vigor and floor. 

    The crew made use of the potential to embed design constraints within the netlist handed between the entrance-end design team and the implementation team.  Up unless that point, those constraints had been communicated by using cryptic notes on the schematic.  as an example:  Specify that two gates obligatory to be matched or a particular internet is critical and its optimum size need to no longer be passed within the layout.  Communicated the ancient manner, when the schematic become given to the implementation engineer, the designer could simplest hope that the implementation crew achieved the favored effect. 

    Managing Complexity

    The implementation crew built a brand new memory with the aid of making a single memory mobile then replicated it to build the more complicated arrays — a bottom-up approach versus the general right-down approach that tremendous digital SoC design groups make use of.  The reminiscence consisted of somewhat cell comprising two transistors.  

    once the bit mobilephone was created and optimized, the telephone became replicated along a horizontal line of size n (32, for instance), as distinct in the schematic.  once the line of reminiscence cells became created, it turned into replicated vertically m number of rows (32, as an example), as targeted in the schematic.  during this method, the implementation engineer created a 1-Mb reminiscence array.  The system was repeated three more instances to create the 4-Mb memory, a two-via-two matrix of 1-Mb arrays.

    In setting up the preliminary netlist, the front-end dressmaker labeled each of the bit cells and its linked vigor, ground, bit line and note line.  He then precise the number of bit cells to be powered by way of a given energy internet to make certain that each phone obtained the equal quantity of present.

    The capacity to set constraints in the netlist passed to the implementation engineer ensured the design intent became captured in closing layout. 

    Automating Repetitive guide projects

    Automating repetitive projects tremendously decreased the time to complete the layout as neatly.  for example, labeling the bit line, notice line, feel amplifier, and energy and ground for a 4-Mb reminiscence can take appreciable time if done manually.  Surrendering the assignment to the EDA device reduced the chore to a handful of keyboard operations.

    In a pull-down menu, the implementation engineer achieved a form that asked for the signal identify, variety of pins to be labeled, x and y coordinates of the first signal, spacing between pins, and the measurement of the text.  From this counsel, the design device created each particular person signal name.

    once the reminiscence IP become applied for the 40-nanometer (nm) technique at foundry A, the layout crew turned into confronted with converting the reminiscence to 40 nm at one other foundry.  With the automated EDA stream, this was decreased to a two-step procedure:  layer mapping followed by statistics manipulation.  in the first step, the mapping table for foundry A’s forty-nm library become changed with the mapping desk for foundry B’s 40-nm library.  The tool then immediately produced a layout for foundry B.  The method became not absolutely automatic, as every foundry has its own exciting rules; hence exceptions that don't map one-to-one are highlighted.

    The implementation engineer examined all generated exceptions then made fundamental alterations.  as an instance, in foundry A, the bit phone might also use layer C and D, whereas in foundry B, layer D and E are used.  once the conversion changed into accomplished, a design rule examine (DRC) become performed along with remaining verification. 

    This automation took half the time compared with ranging from scratch, enabling rapid migration of IP from one foundry to an additional.  while designing new memory IP, such as Kilopass’ Gusto anti-fuse NVM, continues to be more often than not a guide effort, facets may also be automated, enabling the layout and implementation group to concentrate on critical analog features that must be tailor-made for a person foundry and process.  

    creator Bio:  Bernd Stamme is Director for advertising and functions at Kilopass know-how.  He has more than 15 years of experience within the IP and semiconductor industry. prior to Kilopass, he become the Director of IP know-how at SiRF technology managing the licensing and a success integration of third-celebration IP into SiRF’s GPS chip units.  earlier than SiRF, he held administration positions in LSI logic’s CoreWare organization and worked on high-pace SerDes IP, communication interfaces and processor core.  Stamme holds a Dipl.-Ing. degree in Electrical Engineering from FH Bielefeld in Germany.


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    LSI SVM5 Implementation Engineer

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    A Design Methodology for Building Process-Independent Hardmacro IP | killexams.com real questions and Pass4sure dumps

    Rapidly migrating intellectual property (IP) from one foundry to another and from one process node to the next can be a challenging, but necessary, part of the business, especially if the IP is generated and delivered as hardmacro IP.  That’s because hard IP or a GDSII netlist versus soft IP, RTL or gate-level netlist must be available for all major foundries and for a wide selection of process nodes at each foundry.

    Designing new memory IP is largely a manual task that involves more analog circuits —charge pumps, voltage regulators and sense amplifiers, for example — than most logic designs.  At four megabytes (Mb), the design burden facing the layout manager and his implementation team is formidable. 

    These issues are typical of memory design, and the Kilopass team ran into them when designing a recent 4-Mb memory IP block.  Its experience offers ways in which other teams can overcome these challenges.

    To ease the burden, the team identified elements of the design that could be automated, freeing them to concentrate on critical analog elements that must be tailored for an individual foundry and process.  The result is an electronic design automation (EDA) tool flow developed for the latest anti-fuse non-volatile memory (NVM) product line. 

    Exploiting the EDA Tool Flow

    Using commercially available EDA solutions, the first task to be automated was rapid and accurate entry of design concepts, including managing design intent in a way that flowed naturally in the schematic.  This allowed designers to visualize and understand the many interdependencies of an analog or mixed-signal design and its effects on circuit performance.

    In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by another internal team.  The task of merging the existing layout with the rest of the memory design was a simple process requiring a day of manual place and route or connecting I/Os and routing power and ground. 

    The team made use of the ability to embed design constraints in the netlist passed between the front-end design team and the implementation team.  Up until that point, those constraints were communicated by cryptic notes on the schematic.  For example:  Specify that two gates needed to be matched or a specific net is critical and its maximum length must not be exceeded in the layout.  Communicated the old way, when the schematic was given to the implementation engineer, the designer could only hope that the implementation team achieved the desired result. 

    Managing Complexity

    The implementation team built a new memory by creating a single memory cell then replicated it to build the more complex arrays — a bottom-up approach versus the conventional top-down approach that large digital SoC design teams employ.  The memory consisted of a bit cell comprising two transistors.  

    Once the bit cell was created and optimized, the cell was replicated along a horizontal line of length n (32, for example), as specified in the schematic.  Once the line of memory cells was created, it was replicated vertically m number of rows (32, for example), as specified in the schematic.  In this manner, the implementation engineer created a 1-Mb memory array.  The process was repeated three more times to create the 4-Mb memory, a two-by-two matrix of 1-Mb arrays.

    In developing the initial netlist, the front-end designer labeled each of the bit cells and its associated power, ground, bit line and word line.  He then specified the number of bit cells to be powered by a given power net to ensure that each cell received the same amount of current.

    The ability to set constraints in the netlist passed to the implementation engineer ensured the design intent was captured in final layout. 

    Automating Repetitive Manual Tasks

    Automating repetitive tasks greatly reduced the time to complete the layout as well.  For example, labeling the bit line, word line, sense amplifier, and power and ground for a 4-Mb memory can take considerable time if done manually.  Surrendering the task to the EDA tool reduced the chore to a handful of keyboard operations.

    In a pull-down menu, the implementation engineer completed a form that asked for the signal name, number of pins to be labeled, x and y coordinates of the first signal, spacing between pins, and the size of the text.  From this information, the design tool created each individual signal name.

    Once the memory IP was implemented for the 40-nanometer (nm) process at foundry A, the layout team was confronted with converting the memory to 40 nm at another foundry.  With the automated EDA flow, this was reduced to a two-step process:  layer mapping followed by data manipulation.  In the first step, the mapping table for foundry A’s 40-nm library was replaced with the mapping table for foundry B’s 40-nm library.  The tool then automatically produced a layout for foundry B.  The process was not completely automated, as each foundry has its own unique rules; thus exceptions that do not map one-to-one are highlighted.

    The implementation engineer examined all generated exceptions then made necessary adjustments.  For example, in foundry A, the bit cell may use layer C and D, whereas in foundry B, layer D and E are used.  Once the conversion was completed, a design rule check (DRC) was performed along with final verification. 

    This automation took half the time compared with starting from scratch, enabling rapid migration of IP from one foundry to another.  While designing new memory IP, such as Kilopass’ Gusto anti-fuse NVM, continues to be mostly a manual effort, elements can be automated, enabling the layout and implementation team to concentrate on critical analog elements that must be tailored for an individual foundry and process.  

    Author Bio:  Bernd Stamme is Director for Marketing and Applications at Kilopass Technology.  He has more than 15 years of experience in the IP and semiconductor industry. Prior to Kilopass, he was the Director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets.  Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core.  Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.


    LSI Industries: Planning For A Bright Future | killexams.com real questions and Pass4sure dumps

    No result found, try new keyword!LSI Industries' share price has declined significantly in the ... We should note, in addition, that the author of this article is himself a licensed professional architectural engineer who has specifi...

    Video Encoding: Go for the Specialist or the Jack-of-All-Trades? | killexams.com real questions and Pass4sure dumps

    One of the hardest choices encoding technicians have to make is deciding between hardware and software. Hardware-based encoders and transcoders have had a performance advantage over software since computers were invented. That's because dedicated, limited-purpose processors are designed to run a specific algorithm, while the general-purpose processor that runs encoding software is designed to handle several functions. It's the specialist versus the jack-of-all-trades.

    In the past few years, processors and workflows have changed. The great disruptor has been time and the economics of Moore's Law, which famously says that the number of transistors incorporated in a chip will approximately double every 24 months. The logical outcome of Moore's law is that the CPUs get more powerful by a factor of two every few years, but more recently processing power seems to double every few months. Lately, Intel -- whose co-founder Gordon Moore coined Moore's Law -- has been adding specialty functions along with its math co-processors to equalize the differences between general-use processors and specialty processors.

    There are many layers and elements to both a general-purpose processor and a task-specific hardware processor. The general-purpose CPU is the most common -- there are literally billions of them in all manner of computing devices -- while the more purpose-oriented processors include digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and integrated circuits (ICs) that are available for various industrial appliances and widely used in cellphones. Many of the structures and elements are similar across all types, but there are considerable differences. If you are not familiar with the elements of the various types, here are the basic structures of both.

    The General-Purpose CPU

    The general-purpose CPU is laid out with flexible core elements as the arithmetic logic unit (ALU), control unit (CU), and accessory elements that offer extra features for performance. Basically these two cores talk to each other, bring in memory as needed, and send work to the other elements. Other elements include I/O processors, logic gates, integrated circuits, and -- on most newer processors and especially on the Intel Xeon processors -- a beefy math co-processor. The math co-processor assists the ALU and can handle the more extreme and complex mathematical computations. Essentially, it gives the processor the extra horsepower it might require.

    The Dedicated Processor

    Specific-purpose hardware encoders have been around longer than general-purpose processors, and the latter have been slower at mathematical equations or algorithm problems. History is vitally important to understand the market and technology, not to mention get a sense of what the future holds. The earliest example of encoding was in 1965, when the Intelsat 1 (Early Bird) became the first commercial deployment of a satellite to downlink video and audio. Since then, the world has been using specific processors to process video, and the technology has made leaps and bounds to offer higher density and quality.

    Video ARM DSP

    This is a general layout of a video ARM DSP. The ARM core runs the embedded operating system, working like a traffic cop to control input and output. 

    Dedicated processors -- such as dedicated signal processors (DSPs), graphics processing units (GPUs), and vector processors -- all have a very similar design structure. A basic and most common element is an I/O manager, which has a tiny onboard operating system along with memory. This is the traffic cop, controlling input and output. Then there are multiple specialized processing modules that execute the desired instructions very quickly and that DSPs and other dedicated processors support. Unlike a general-purpose processor, which has many possible general instructions that may not be most efficient for the task at hand, dedicated processors rely on accelerated, per-function instructions that are more job-specific.

    Dedicated processors and encoders have a variety of applications and workflows. If you look at the major users of professional encoders, you will see that in many cases they rely on specialized encoders. The following well-known companies make DSP chips: LSI Corp.; Texas Instruments, Inc.; Analog Devices, Inc.; Sony; and Magnum Semiconductor. These DSPs are used in devices such as media gateways, telepresence devices, cellphones, and military and radar processing.

    FPGAs are now very popular implementations of DSP functions because of their flexibility of setup and upgrade. Since they are field-upgradeable, their development costs for the user are significantly cheaper than DSPs and application-specific integrated circuits (ASICs; more on those in a moment) from the traditional DSP providers. You can see FGPAs from Altera Corp. and Xilinx, Inc. that have DSP functions built in. If you want a board or system that is easier to upgrade in the field, then this is probably the best way to go.

    DSP Packets

    While each manufacturer will tweak its design slightly, this is an overview of how communications and packets flow into the modules of DSPs and ASICs. 

    Another implementation of the dedicated processor is the ASIC. These factory-programmed DSPs are used everywhere cost is a crucial consideration, because they offer special functionality at optimal price and performance. In general, they are more expensive to design but are cost-effective for any appliance or board manufacturer to implement into their systems. Many manufacturers of DSPs also manufacture ASICs; companies such as NXP Semiconductors, Broadcom Corp., and Freescale, Inc. also make custom ASIC DSPs.

    If you ever open up a hardware encoding appliance -- from IP media gateways to broadcast encoder and decoders -- you will see several of the chips previously listed. You can find appliances for every industry. Today you will find a dedicated hardware-based encoding device from Harmonic, Inc.; Harris; Tandberg Data; or NTT Communications in every TV station or cable TV headend, and you'll find appliances or cards from ViewCast Corp. or Digital Rapids in many hybrid encoding farms, since they accelerate some of the functions in the hardware. If you've watched a video on YouTube, then you have seen video encoded by RGB Networks with the RipCode equipment, which used massive numbers of Texas Instruments, Inc. DSPs.

    Pros and Cons of Hardware Encoders

    There are always some pros and cons when it comes to specific design hardware encoders and dedicated appliances. The dedicated hardware approach with DSPs or chips is the perfect solution for media gateways and in low latency military applications. They are designed to run 24/7 with little or no human interaction. There are some processors that can encode an entire frame in the 1ms-10ms (millisecond) range and FPGAs that can encode in the 10ms-30ms range. These processes allow for the creation of appliances where the encoding latency is less than 100ms from encode to transmission to decode. Right now you can only get low latency using the right DSPs, ASICs, and FPGAs. The average lifespan of an appliance is 5-10 years depending on the configuration and manufacturer. Similar lifetimes are assumed for systems that rarely change, such as satellite uplink or cable system encoders.

    The primary drawback of dedicated hardware-based encoding is that the codec on the processor is generally impossible to upgrade. Every DSP, ASIC, or FPGA is based on an algorithm that was finalized years ago. By the time the chip is ready to be sold, the codec is 6 months to a year old. Add more design cycles for the appliance development and manufacturing, and the end result is a device based on a codec that's a year or more old. If improvement to the codec comes out, the chip or device might never be able to integrate the new codec or technology due to the manufacturer or the way the chip was designed. The dedicated DSP approach can save a lot of money, but at the expense of flexibility. Those chips do just what they were originally designed to do and nothing more.

    Hardware Encoder

    Video comes into a hardware encoder to a media gateway, which will make adjustments to the video stream to address network conditions and the end user’s video decoding device. When done, it will send these modifications to the video decoder. 

    There's another issue with dedicated chip-based encoders: Who determines the quality of the codes and streams? Is it a DSP engineer, a compressionist, or the producer and director? In a TV station, it's usually a combination of chief engineer and executive producer who decide what station image goes over the air. If they use a hardware encoder, in many cases decisions about encoding parameters have been taken out of their hands. The broadcast engineer has to work within the parameters the chip manufacturer has allowed end users to change, meaning that while there is usually some control, there may not be as much as a producer or engineer would like. There are only so many operations and cycles you can put on a chip, so some functionality is uneconomical to implement.

    The Pros and Cons of Software Encoders

    General-purpose CPUs share some similarities and architecture with dedicated processors. They are designed to handle the everyday functions of your PC or server, and they are optimized to do mundane tasks such as word processing. This is why your motherboard has a powerful graphics card in your machine; it's a specialty function that is best offloaded to a specific-designed processor. If you do any nonlinear video editing, you likely have a capture card with some specialty processors to give you real-time output or transitions.

    In the encoding and streaming industry, we mostly use a capture board and one or more of many available software encoding packages. There are algorithms and formulas for every application, from live encoding to file-based transcoding to software-based decoding. These days most software-based encoders have hooks in the code to offload certain elements to accelerate or allow multiple CPUs to run parallel functions to get the best performance and quality. More recently, Intel is offering some onboard GPUs that feature decoding with MPEG, analysis of a video stream's motion vectors, and other functions.

    GPU

    This overview shows how a GPU or video accelerator is laid out. Again, one device works as a traffic cop to send work to the appropriate processors, then takes the video streams back and reassembles them together, allowing video to be encoded at a faster rate. 

    Software encoders have allowed users to be much more flexible in responding to the needs of specific customers or events, and they all use the same general-purpose processors and capture boards to support more video formats and standards. This has been an advantage for software encoders for a long time. They are easy to reconfigure and use.

    The software encoding industry has recently seen battles between open source and closed source. There are some notable pioneering closed source companies that helped drive the development of software encoding and streaming: Microsoft; Real Networks, Inc.; Sorenson Communications; and Adobe Systems, Inc. laid out the framework for modern streaming and web-based video. They have been around since the beginning, and in many cases they financed the codecs that became standards.

    In addition to these pioneering companies, there has been a recent movement to open source. Some of the earlier versions such as x264 and the open source library in the University of California-Berkeley provide the foundation for most software encoders. Code is added every so often and allows others to program their custom apps. The better-known ones such as VideoLan (VLC), FFmpeg, and WebM are creating new versions and are catching on in general use. Some are even getting funding from some of the larger public companies. The most notable example is WebM, which is being funded mostly by Google, which made the VP8 codec open source after it acquired On2 Technologies. All this competition and activity is creating better products for consumers. The big companies realize open source development and innovation is faster-moving than their own, allowing the market to grow more quickly than it otherwise might.

    But software-based encoding has some drawbacks. The most important parameters of encoding are quality, flexibility, price, latency, and support.

    Software encoding's greatest advantages over pure hardware encoders are its flexibility and quality. Software has always been able to adopt and update incredibly fast. When new codec optimizations come out, encoding package updates follow very soon after.

    Software encoding can enable the producer, engineer, or other user to get precisely the quality and image that they want, unlike the automated hardware solution, where the user has no say in what the overall image is and outcome will be. Some larger encoding firms hire color consultants and compressionists, along with programmers and delivery experts, all of whom help the executive producers and directors determine what the overall outcome should look like. It's a broadcast approach for streaming.

    Xeon Phi

    Later this year or in early 2013, Intel will release its Xeon Phi series of massive parallel coprocessors, which will work with existing Xeon processors and workflows. 

    So if software encoding wins in flexibility and quality, what about speed or latency? While some highly tuned hardware encoders offer a latency down in the 30ms range, most software solutions run in the 300ms-500ms range, if not higher. Most people who use software encoding realize they are sacrificing some speed for quality. All that matters is whether or not they can get the resolution and framerate they want; if it's delayed some, the workflow can be designed to accommodate it. On the other hand, if you require the lowest latency and fastest delivery, you will have to give up some quality.

    Cost of support is of course an important issue. Will the proprietary company keep making the version you're using, or is there a chance it will be withdrawn from the market? How much will the updates and upgrades cost? It turns out that upgrades in the open source community are relatively frequent, whereas upgrades in propriety software are less so.

    While some people assume that open source products offer lower quality or reliability than proprietary software, that's not necessarily the case. FFmpeg, VLC, and WebM are all significantly upping their quality. On the other hand, proprietary software packages such as Sorenson and MainConcept have also stood the test of time and continue to find widespread use. Interestingly, MainConcept and Sorenson are two of the few companies whose solutions are used in both software and hardware encoding; both provide codecs for the PC environment as well as specifically designed chips.

    Changes in Media Consumption, Changes in Media Encoding

    General-purpose hardware-based decoders are now playing an important role in the overall media viewer world, especially as more and more viewers are quitting cable and going the IP route for all of their video consumption. Roku, Boxee, and other IP set-top boxes are DSP-based decoders. At the same time, more and more consumers are adopting Android or iOS devices and using them as personal media players, and each device brings with it its own set of ideal encoding profiles and parameters. You'll find you need to do custom scaling and probably want to offer the highest possible complexity. Then again, you need to spend more CPU cycles per frame, which will require more encoding time but create a better outcome.

    Conclusion

    There will always be a battle between hardware encoding and software encoding. Who will win in various market segments? Why a hardware encoder versus the software encoder? Even now we are starting to see more specialty functionality appended on the general-purpose CPUs, due to the miniaturization and density of transistors and processors. For instance, Intel recently agreed to buy 190 patents and 170 patent applications from RealNetworks, and for years the company has been adding graphics processing and other accelerators or processing engines.

    Dedicated hardware encoding wins in unique parallel processing situations when massive amounts of data need to be processed, as well as in low latency communications such as real-time financial and some military applications. It also leads in situations where you want to just install the encoding tool and let it do its thing, such as in situations with YouTube that can rely on automated, predefined resolutions and bitrates for a massive amount of viewers. But software encoders will be the tool of choice in most applications. It's faster and cheaper to encode with software than in hardware, and once you see how the market responds to your output, it's faster and cheaper to make modifications.

    So, do you most value flexibility and lower costs? Then software is probably your best bet. Do you need low latency and stream density or automated auto-transcoding for the mobile market? Then a hardware solution probably is best for you.

    This article appears in the October/November, 2012, issue of Streaming Media magazine under the title "The Specialist Vs. the Jack-of-All-Trades."

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    References :


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