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FN0-240 Foundry Networks Certified Layer4-7 Professional

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FN0-240 exam Dumps Source : Foundry Networks Certified Layer4-7 Professional

Test Code : FN0-240
Test Name : Foundry Networks Certified Layer4-7 Professional
Vendor Name : Foundry
Q&A : 270 Real Questions

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Foundry Foundry Networks Certified Layer4-7

Brocade licensed community knowledgeable (BCNP) | Real Questions and Pass4sure dumps

This seller-certain Certification is obtainable with the aid of:Brocade Communications systems, Inc.San Jose, CA USAPhone: 408-333-8000Email: This e-mail tackle is being covered from spambots. You need JavaScript enabled to view it.

skill level: advanced                          repute: active

reasonably priced: $150 (shortest song)               

abstract:for people who installation, configure, keep, and troubleshoot Brocade Ethernet switches and routers in complicated environments.

preliminary necessities:You need to move the Brocade licensed network expert exam ($one hundred fifty). The exam contains 60 questions and has a 90 minute time limit. A passing score of 60% is required.

it's advised you attend the primary swap Router and Configuration administration course and hold a Brocade licensed network Engineer certification.

carrying on with requirements:Brocade certifications are edition specific, so your certification is on a selected product edition and thus will by no means expire.

See all Brocade Certifications

vendor's page for this certification

Foundry Networks Continues Its MPLS management on the 10th Annual MPLS 2007 overseas conference | Real Questions and Pass4sure dumps

October 25, 2007 15:13 ET | source: Foundry Networks, Inc.

SANTA CLARA, Calif. and WASHINGTON, Oct. 25, 2007 (prime NEWSWIRE) -- Foundry Networks(r), Inc. (Nasdaq:FDRY), a efficiency and complete options chief for end-to-end switching and routing, today announced that it's exhibiting and collaborating in two classes on provider Ethernet features and MPLS load sharing at the tenth annual MPLS 2007 overseas conference in Washington, D.C. in addition to the technical sessions, Foundry can be exhibiting its award-winning NetIron(r) XMR 32000 spine router and service company infrastructure and options in sales space 102. MPLS 2007 will take place from Oct. 28 to 31, 2007 at the Omni Shoreham hotel in Washington, D.C.

the primary session will characteristic Foundry's Ahmed Abdelhalim and discuss service Ethernet features. The 2nd session will center of attention on boosting capability utilization in Multiprotocol Label Switching (MPLS) networks the usage of load sharing. in this presentation, Foundry's Sanjay Khanna will seem on the reasons for load sharing, the a considerable number of layers the place load sharing is used, highlight the standards used for load sharing at each layer and advocate the top-quality schemes for use for each site visitors type to boost network capacity utilization. he will extra spotlight pleasing strategies of speculation in MPLS packets and neutralizing polarization outcomes.

Session: "vendor Panel Session: service Ethernet functions" Participant: Ahmed Abdelhalim, director of product advertising, Foundry Networks Time & Date: 5:00 p.m. - 6:00 p.m. EDT, Tues., Oct. 30, 2007 vicinity: Omni Shoreham resort, Washington, D.C. Session: "Boosting ability Utilization in MPLS Networks the use of Load Sharing" Speaker: Sanjay Khanna, senior product marketing manager, Foundry Networks Time & Date: 11:00 a.m. - 12:30 p.m. EDT, Wed., Oct. 31, 2007 place: Omni Shoreham resort, Washington, D.C.

Foundry has leveraged greater than 10 years of routing and switching experience and greater than five years of MPLS adventure to increase its fifth generation of Terabit-scale MPLS routers, the NetIron XMR series and NetIron MLX sequence. Foundry's MPLS solutions are can charge- and performance-optimized for advanced functions in metro edge, aggregation, records facilities and cyber web core routing.

The NetIron family unit of routers from Foundry makes use of a extremely allotted routing structure to convey feature-rich, wire-velocity performance in IPv4/v6/MPLS functions. These systems enable the birth of superior services over a converged IP/MPLS-based infrastructure. Backed by using the intelligence in Multi-provider IronWare(tm) working device utility, Foundry's NetIron family of routers offer quite a number solutions equivalent to point-to-aspect Layer 2 MPLS VPNs (virtual Leased Line, VLL), Multi-factor Layer 2 MPLS VPNs (virtual private LAN carrier, VPLS), Layer three MPLS VPNs (RFC2547bis), and MPLS site visitors engineering and IP over MPLS.

For extra information, please talk over with Foundry in booth 102 or seek advice from

About Isocore

Isocore gives technology validation, certification and product comparison services in emerging and subsequent-technology cyber web and wireless applied sciences. Isocore is leading validation and interoperability of novel applied sciences together with service Ethernet, IPv6, IP Optical Integration, instant backhauling and Layer 2/3 digital deepest Networks (VPNs), and currently specializes in IPTV service deployment architecture validation and design. fundamental router and switch providers, carrier suppliers, and check device suppliers participate in Isocore activities. Isocore has predominant places of work in the U.S., Europe and Asia.

About Foundry Networks

Foundry Networks, Inc. (Nasdaq:FDRY) is a number one issuer of high-efficiency business and service issuer switching, routing, safety and net traffic administration options, together with Layer 2/three LAN switches, Layer 3 backbone switches, Layer 4-7 application switches, instant LAN and access elements, metro and core routers. Foundry's purchasers include the world's premier ISPs, metro provider suppliers, and organisations, together with e-commerce sites, universities, entertainment, health and wellness, govt, economic and manufacturing agencies. For greater tips about the company and its items, call 1.888.TURBOLAN or visit

The Foundry Networks, Inc. emblem is purchasable at

Foundry Networks Media Contact: Pavel Radda 408.207.1332 FD Investor Contact: Brendan Lahiff 415.293.4425

Syntel Selects Foundry Networks to give Infrastructure for new Campus community upgrade | Real Questions and Pass4sure dumps

Foundry solutions Deployed as the groundwork for at ease, high-velocity Campus community

SAN JOSE, Calif., Jan. 24 /PRNewswire-FirstCall/ -- Foundry Networks(R), Inc. (NASDAQ:FDRY), a performance and total options chief for conclusion-to-end switching, routing, and web traffic management options, these days introduced that Syntel, Inc. (NASDAQ:SYNT), a worldwide tips technology functions company, chosen Foundry's high-performance switching and routing solutions to energy it be new international building middle (GDC) in Pune, India. Syntel's vertical practices aid the total Design-construct-operate-Optimize lifecycle of techniques and methods for enterprises in the financial services, coverage, retail, fitness care and transportation industries.

Foundry Networks become chosen for Syntel's network infrastructure on account of its proven track checklist at Syntel's GDC in Chennai, India and for the business's skill to deliver low-latency, authentic, and scalable solutions. Foundry's award-winning BigIron RX household of high-efficiency routing switches will energy Syntel's community core on the new campus, which accommodates more than 7,000 engineers. The BigIron RX family unit points redundant change fabric, gadget management, and power provide add-ons to be certain highest reliability. it's the industry's first a hundred-Gigabit Ethernet (one hundred-GE) competent change fabric with the maximum wire-speed 10-GE and GE port densities available nowadays. The FastIron(R) SuperX collection switches equipped with 10-GE uplinks will supply excessive-capability aggregation for Syntel, while the FastIron part X collection switches fitted with power-over-Ethernet (POE) will allow full Layer 2/3 intelligence at the community's edge. Foundry's FastIron WLAN POE switches and IronPoint(TM) access elements can be deployed throughout Syntel's campus to give users with comfy, excessive-velocity, and simple-to-manage wireless LAN features. Foundry's ASIC primarily based sFlow implementation will supply Syntel with superior community monitoring, auditing, and intrusion detection capabilities. The community has been designed conclusion-to-conclusion with particularly accessible, resilient, and redundant aspects to make sure business continuity.

"community reliability and scalability are crucial not simplest to Syntel, but to our Fortune 500 valued clientele who we serve through our international construction centers," pointed out Sajid Ahmed, world head of infrastructure for Syntel. "when we begun taking a look at network switch options for our new forty-acre state-of-the-artwork campus in Pune, India, Foundry Networks passed our expectations. they have the business's most advanced layer 2 and three networking machine, each when it comes to structure and performance. We were also impressed with the means to give an open-ended and scalable answer. Foundry now not most effective met our aspects necessities, but also prevailed in decreasing our total cost of possession and future-proofing Syntel's network investment."

The FastIron facet X collection switch with POE (FESX-POE) establishes the benchmark in edge connectivity via delivering essentially the most adaptable function set combined with the maximum quantity of power accessible for POE device support. a total of 480 watts dedicated to POE set a new benchmark for the industry by means of supplying up to fifteen.4 watts for each 10/one hundred/one thousand Mbps port the usage of a single energy provide in a hard and fast configuration; the option for a second inner redundant power supply delivering 100% system and POE redundancy is attainable. to fulfill current and rising network necessities, the FESX-POE systems provides a complete set of requirements-based, feature-prosperous Layer 2 switching and Layer three multiprotocol routing capabilities, comprehensive hardware and utility redundancy, comprehensive fine-of-service (QoS) controls, and built-in copper Gigabit Ethernet ports. The wide feature set helps community requirements ranging from simple connectivity to multicast-enabled full streaming audio and video purposes for converged features, together with Voice over IP (VoIP).

Sajid introduced, "so as to configure different providers' POE switches with redundant vigour, we needed to retrofit an exterior vigour provide which is not simplest inefficient, but additionally expensive. because Foundry constructed POE and redundant vigor capabilities into the FastIron aspect X series switches and made it sizzling swappable, we obtained extra switching power and performance for our cash than with every other alternative available on the market."

D-hyperlink India will give the native technical capabilities, installing and integration services to aid design and deploy the Foundry community at Syntel campus.

"D-link India is proud to partner with Foundry Networks and work with Syntel to install their state-of-the-paintings LAN Infrastructure," stated k. R. Naik, Chairman and Managing Director, D-link India restricted, Foundry's main associate in India. "We purpose to leverage our networking and communications talents to provide Syntel the premiere community infrastructure integration experience feasible."

"Foundry is breaking new ground by integrating the primary 100 Gigabit-ready switch in India," noted Chandra Kopparapu, vice president of earnings for Asia Pacific, at Foundry Networks. "We appear ahead to working with Syntel as they continue to develop and diversify their enterprise."

About Foundry Networks

Foundry Networks, Inc. is a leading provider of high-efficiency enterprise and repair company switching, routing, security and web traffic administration solutions including Layer 2/3 LAN switches, Layer three backbone switches, Layer 4 - 7 application switches, wireless LAN and entry features, access routers and metro routers. Foundry's 8,900 purchasers encompass the world's premier ISPs, metro carrier suppliers, and organisations together with e-commerce websites, universities, entertainment, fitness and wellbeing, executive, monetary, and manufacturing groups. For more assistance in regards to the business and its items, name 1.888.TURBOLAN or consult with

About Syntel Inc.

Syntel, Inc. offers assistance technology (IT) capabilities serving fiscal, manufacturing, healthcare, transportation, retail, and information/communication industries global. It operates in 4 segments: purposes Outsourcing, e-business, TeamSourcing, and business system Outsourcing (BPO). Syntel became the primary US-primarily based enterprise to launch a worldwide start service to power velocity-to-market and fine benefits for its shoppers. Syntel's 5,500+ personnel function from facilities within the US, Europe, and Asia. Syntel became established in 1980 and is headquartered in Troy, Michigan.

About D-link India Ltd.

D-link (India) Ltd. is part of the multinational D-link employer, which has a presence in over a hundred nations. Its core company is within the area of networking and communications. D-hyperlink India's product range enjoys mammoth market share in India and ranks among the many leaders in Modems, Structured Cabling, wireless LAN and Switches.

D-link (India) has a strong infrastructural presence with ISO 9001:2000 and ISO 14001:1996 licensed state-of-the-artwork manufacturing plants in Goa; application and R&D facilities in Goa and Bangalore; and a world Tech support name core in Mumbai. It has a nationwide network of 17 offices, 21 territory distributors, 400+ dealers and 4000+ resellers and four distant places distributors in SAARC international locations providing energetic earnings and service help.

Media and Investor family members Contacts:

North AmericaPavel RaddaFoundry

connected Thomas trade update Thomas For Industry

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Cisco CCIP MPLS certification: Introduction | real questions and Pass4sure dumps

Learn skills required for the MPLS portion of the Cisco CCIP certification. These skills are tested in the CCIP 642-611 -- Implementing Cisco MPLS Exam.

In the articles that follow, I am going to talk about foundational skills required to achieve MPLS certification. In reality there is no MPLS certification. MPLS skills are generally considered a subset of the skills required for multiple vendor certifications including Cisco's Certified Internetworking Professional (CCIP), Juniper Networks Technical Certification Program (JNTCP) and Foundry's Network Certification Program (FNCP). While these vendor certifications represent the major certifications surrounding MPLS, in reality, Cisco and Juniper dominate the deployed base for carrier solutions. I would recommend that those interested in certification pursue either Cisco or Juniper certifications.

Regardless of which vendor's certifications you eventually pursue, there are going to be concepts related to MPLS technology that will be common across all of the certifications. These concepts are what I consider the foundation skills for having a complete understanding of MPLS technology in order to be considered an expert in the field. The key areas of focus are as follows:

If you can gain a good understanding of all of these topics, not only will you be well versed in MPLS technology, but you will be prepared for any certification exam that requires MPLS expertise.

Cisco Certified Internetworking Professional (CCIP) certification requires an understanding of these topics as well as an understanding of how to implement these technologies. Subsequent articles will provide a brief overview of the technology and specific configurations for enabling the technology on Cisco platforms. The intent is to provide the foundational skills required to pass the CCIP exam 642-611 -- Implementing Cisco MPLS Exam. This exam is one of three to four exams required to achieve CCIP certification. The reason I say three to four exams is that Cisco provides a dual track to CCIP certification. Check for an outline of the CCIP certification requirements.

I will not be writing any articles outlining the technology or skills required for the other certification tests, only for the MPLS portion of the exam. It is my intent to provide a solid foundation of MPLS skills that can be used to pass the MPLS exam.

About the author:Robbie HarrellRobbie Harrell (CCIE#3873) is the National Practice Lead for Advanced Infrastructure Solutions for SBC Communications. He has over 10 years of experience providing strategic, business, and technical consulting services to clients. Robbie resides in Atlanta, and is a graduate of Clemson University. His background includes positions as a Principal Architect at International Network Services, Lucent, Frontway and Callisma.

Southland Steel Investing $18M In Louisiana Expansion | real questions and Pass4sure dumps

Southland Steel Fabricators Inc. will expand to a second Louisiana site, creating new fabrication and coating lines with a $18 million capital investment at the former Bradken foundry in Amite, Tangipahoa Parish. The Greensburg-based company’s expansion will create 70 new direct jobs, and retain 176 existing jobs that are based at the company’s St. Helena Parish headquarters and manufacturing site.

Amite, Tangipahoa Parish, LA(Source: Southland Steel Fabricators Inc.)

“Southland Steel is extremely excited about expanding into Tangipahoa Parish, working with local government and becoming part of the Amite community,” said Southland Steel President/Owner Joey Lombardo. “This expansion will more than double our square feet under roof to over 650,000, and we will have 110 acres between the two locations. Our overhead crane-lifting capacity is now over 750 tons, with cranes ranging from 5 to 65 tons each. We look forward to utilizing this facility to expand our business, grow our customer base, and better serve our customers by vertically integrating our supply chain and strategically expanding our operations.”        

Louisiana Economic Development (LED) estimates the project also will result in an estimated 111 new indirect jobs, for a total of more than 180 new jobs in Tangipahoa Parish and surrounding areas.

“Since 1986, Southland Steel has built a homegrown business in St. Helena Parish into one of the fastest-growing steel fabricators in the nation,” said Gov. Bel Edwards. “Not only is Southland Steel growing, but it is now helping to revive the Amite foundry that succumbed to difficult challenges during the oil and gas downturn earlier in the decade. This is a company that has focused its fabrication on technology, training and quality control, and those efforts have produced an outstanding workforce for the future.”

LED began formal discussions with Southland Steel about the expansion project in September 2018. To secure the project, the State of Louisiana offered the company a competitive incentive package that includes the LED FastStart® workforce training program. The company also is expected to utilize the state’s Quality Jobs and Industrial Tax Exemption programs.

“LED, Tangipahoa Economic Development and our regional workforce partners have done an excellent job assisting Southland Steel in making this decision to expand into Tangipahoa,” said Executive Director Ginger Cangelosi of the Tangipahoa Economic Development Foundation. “These 70 new jobs will be a promising addition to our already growing workforce. We thank the Lombardo family for their commitment to Louisiana and Tangipahoa Parish.”

To fabricate precision structural components for customers, Southland Steel has invested heavily in state-of-the-art fabrication equipment, including the first robotic assembly-and-welding system in the U.S. at its 300,000-square-foot complex on 60 acres in Greensburg. The company offers a fabrication capacity in excess of 30,000 tons annually, with 3D modeling software, high-capacity cranes and professional engineering teams. Southland Steel also is the only U.S. steel fabricator certified to apply intumescent fireproofing, lightweight-cement fireproofing and cryogenic coatings in-house.

Louisiana-related projects for whom Southland Steel has fabricated thousands of tons of steel include: Louisiana Sugar Refining; Shintech; ExxonMobil; CF Industries; Sasol; Marathon; Formosa Plastics; SNF Flopam; Valero Refining; Occidental Chemical, or OxyChem; and Honeywell. In Amite, Southland Steel will invest in additional state-of-the-art equipment to expand its steel fabrication and coating services.

“This is a tremendous opportunity for Southland Steel and Tangipahoa Parish,” said Tangipahoa Parish President Robby Miller. “Southland has been an exceptional company servicing customers worldwide from St. Helena Parish, and now this Tangipahoa location will help expand their reach even further. This acquisition is particularly special because it will be putting this existing facility back into commerce.”

Southland Steel, which recently acquired the former Bradken foundry on U.S. Highway 51 in Amite, will begin operations there in late 2019 using existing staff. The company will add 40 new jobs in 2020 and expand to 70 new jobs by 2023. Initially, Southland Steel will be seeking new equipment operators, machine operators, painters and other skilled personnel.

“GNO Inc. is proud to work with legacy companies like Southland Steel to continue to expand in Tangipahoa Parish and throughout South Louisiana – creating new jobs and better opportunities for folks right here in our community,” said President and CEO Michael Hecht of Greater New Orleans Inc. “We must continue to grow Louisiana-made companies to create a regional economy that thrives for everyone. We commend Southland Steel for its commitment to bring more jobs to the region.”

Relocating or Expanding Your Business In Louisiana

Considering Louisiana for your company’s relocation or expansion project? Check out Business Facilities’ Louisiana Incentives and Workforce Development Guide.

IP Integration: Not a Simple Operation | real questions and Pass4sure dumps

Gabe Moretti, Contributing Editor

Although the IP industry is about 25 years old, it still presents problems typical of immature industries.  Yet, the use of IP in systems design is now so popular one is hard press to find even one system design that does not use IP.  My first reaction to the use of IP is “back to the future”.

For many years of my professional career I dealt with board level design as well as chip design.  Between 1970 and 1990 IP was sold as discrete components by companies such as Texas Instruments, National, and Fairchild among many others.  Their databooks described precisely how to integrate the part in a design.  Although a defined standard for the contents did not exist, a de-facto standard was followed by all providers.  Engineers, using the databooks information would choose the correct part for their needs and the integration was reasonably straight forward.  All signals could be analyzed in the lab since pins and traces were available on the board.

Enters Complexity

As semiconductors fabrication progressed, the board became the chip, and the components are now IP modules.  One would think that integration would also remain reasonably straight forward.  But this is not the case.  Concerns about safeguarding intellectual property rights took over and IP developers were reluctant to provide much information about the functioning of the module, afraid that its functionality would be duplicated and thus they would loose sales.

As the number of transistors on a chip increases, the complexity of porting a design from one process to the next also increases.

Figure 1. Projected number of transistors on a chip

Developers found that by providing a hard macro, that is a module already placed and routed and ready for fabrication by the chosen foundry, was the best way to protect their intellectual rights.  But such strategy is costly because foundries cannot just validate every macro for free.  The IP provider must be in the position to guarantee volume use by the foundry’s customers.  Thus many IP modules must be synthesized.  This means they must be verified.

Karthik Srinivasan Corporate Application Engineer Manager Analog Mixed Signal at Apache Design Solutions, an Ansys company, wrote that “SoC designs today integrate significant number of IPs to accelerate their design times and to reduce the risks to their design closure. But the gap in the expectations of where and how the sign-off happens between the IP and SoC designers create design issues that affect the final product’s performance and release. IP designers often validate their IPs in isolation with expectations of near ideal operating conditions. SoCs are verified and signed off with mostly abstracted or in many cases ‘black-box’ views of IPs. But as more and more high speed and noise sensitive IPs get placed next to each other or next to the core digital logic failure conditions that were not considered emerge. This worsens when these IPs share one or more power and ground supply domains. For example, when a bank of high speed DDR IPs are placed next to a bank of memories, the switching of the DDR can generate sufficient noise on the shared ground network that can adversely affect the operation of the memory.

As designs migrate to smaller technology nodes, especially those using FinFET based technologies this gap in the design closure process is going to worsen the power noise and reliability closure process.”

DDR memory blocks are becoming a greater and greater portion of a chip as the portion of functionality implemented in firmware increases.  Bob Smith, Senior VP of Marketing and Business Development at Uniquify makes the case for a system view of memories.

” DDR IP is used in a wide variety of ASIC and SoC devices found in many different applications and market segments. If the device has an embedded processor, then it is highly likely that the processor requires access to external DDR memory. This access requires a DDR subsystem (DDR controller, PHY and IO) to manage the data traffic flowing to and from the embedded processor and external DDR memory.

Whether it is procured from an external source or developed by an internal IP group, almost all chip design projects rely on DDR IP to implement the on-chip DDR subsystem. The integration techniques used to implement the DDR IP in the chip design can have far reaching effects on DDR performance, chip area, power consumption and even reliability.

Figure 2. A non-optimized DDR implementation

The above fiogure illustrates a typical on-chip DDR implementation. Note that while the DDR I/Os span the perimeter of the chip, the DDR PHYs are configured as blocks and are placed in such a way that they are centered with the I/Os. As shown in the diagram, this not only wastes valuable chip area, but also creates other problems. ”

” A much more efficient way to implement the DDR subsystem IP is to deliver a DDR PHY that is exactly matched to the DDR I/O layout. By matching the PHY exactly to the I/Os, a tremendous amount of area is saved and power is reduced. Even better, the performance of the DDR can be improved since the PHY-I/O layout minimizes skew.”

Figure 3. Optimized DDR block

As process technology progresses and moves from 32 nm to 22nm and then 14 nm and so on, the role of the foundry in the place and route of an entire chip increases.  In direct proportion the freedom of designers to determine the final topology of a chip decreases.  Thus we are rapidly reaching the point where only hardened hard modules will be viable.  The number of viable providers in the IP industry is shrinking rapidly and many significant companies have been acquired in the last three or four years by EDA companies that becoming major providers of IP products.

Synopsys started selling IP around 1990 and has now a wide variety of IP in its portfolio, mostly developed internally.  Cadence, on the other hand, has built its extensive inventory of IP products mostly through acquisition.

Michael Munsey, Director of ENOVIA Semiconductor Strategy at Dassault Systemes points out that there are a number of issues to deal with regarding IP.

1.       IP Sourcing:  Companies are going to need a way to source IP.  They will need access to a cataloging system that allows for searching of both internally developed or under development IP as well as externally available third party IP.

2.       IP Governance: For internally developed IP, there needs to be systems and methodologies for handling the promotion of work in progress to company certified IP.  For both internal and externally acquired IP, there needs to be a process to validate that IP, and then a system to rate the IP internally based on previous use, documentation available, and other design artifacts.

3.       IP Issue Defect and Tracking: Since IP will be in use in multiple projects, a formal system is required to handle issue and defect tracking across multiple projects against all IP.  If one group finds and issue with a piece of IP, all other project groups that are using that IP need to be alerted of any issues found and the plan on resolving the issue.  Ideally this should be integrated into design tools that are used to assemble IP as well.  If a product has already gone out the door with the defective IP, these issues need to managed and corrective actions need to ensue based on any defects found.

4.       IP Security:  There are different levels of protection needed for different types of IP and robust methods must be put in place to ensure the security of IP.   First, company critical IP must be secure, and systems need to be put in place to make sure that the IP does not leave the company premises.  If collaborating with partners, any acquired IP must also be handled so that it is only used in the designs that are being collaboratively designed.  There need to be restrictions on using partner IP in design blocks which in turn can become IP in other designs.  There needs to be a way to track the ‘pedigree’ of IP.

5.   Variant driven platform based design:  Ultimately, for companies to keep up with the shortening market windows and application driven platform design, companies will need to adopt a system where there are base platforms with pre-qualified IP that can be configured on the fly and used a s a starting point for new designs.  These systems would automatically populate a design workspace with the required IP from a company approved catalog as the basis of a new design moving forward.

Integrating the Pieces

Farzad Zarrinfar, Managing Director of the Novelics Business Unit at Mentor Graphics,

provided a synthesis of the problems facing designers.

“For IP Integration, multiple IP like ‘Hard IP’, ‘Synthesizable Soft Peripheral IP’, and ‘Synthesizable Soft processor IP’ with different set of deliverables, use EDA tools for efficient ASIC/SOC designs. Selecting the optimal IP size (such as smallest embedded memory IP) is a critical design decision. While free IP is readily available, it does not always provide the best solution when compared to fee-based IP that provides much better characteristics for the specific applications.

IP integration to achieve smaller die size, lower leakage, lower dynamic power, or faster speed can provide designers with a more optimized solution that can potentially save millions of dollars over the life of the product, and better differentiate their chips in a highly competitive ASIC/SoC marketplace.”

Bill Neifert, Chief Technology Officer at Carbon Design Systems observes.  “Certainly, some designers at the bleeding edge differentiate every aspect of the subsystem and their own IP, but we’re increasingly seeing others adopt whole subsystem designs and then making configuration tweaks. Think black box design and ARM’s big.LITTLE offerings are prime examples of this trend.

Of course, in order to make these configuration changes, designers need to know the exact impact of the changes that they’re making. We see users doing this a lot on our IP Exchange web portal. They will download a CPAK (Carbon Performance Analysis Kit), a pre-built system or subsystem complete with software at the bare metal or O/S level. This gets them up and running quickly but not with their exact configuration. They’ll then iterate various configuration options in order to meet their exact design goals. It’s not unusual for a design team to compile 20 different configurations for the same IP block on our portal and then compare the impact of each of these different models on system performance.

Naturally, all of this impacts the firmware team quite a bit. The software developers don’t need to know exactly what the underlying hardware is doing but the firmware team needs the exact IP configuration. The sooner these decisions can be made, the sooner they can start being productive. Integrating this level of software on to the hardware typically exposes a new round of IP optimizations that can be made as well. Therefore, it’s not unusual for IP configuration changes to happen in waves as additional pieces of IP and software are added to the system.”

Drew Wingard, CTO at Sonics points out that standards matter.  “Because there are many sources for IP, the industry had to create and adhere to standards for integration. From a silicon vendors’ perspective, IP sources include third-party commercial components, internally designed blocks and cores, and customer-designed components. To meet the challenge of integrating IP components from many different places, SoC designers needed communication protocol standards. Communication protocol standards efforts began with the Virtual Socket Interface Alliance (VSIA), continued with the Open Core Protocol International Partnership (OCP-IP), and today reside with Accellera. Of course, our customers need to leverage de-facto standards such as ARM’s AMBA as well.  We owe our ability to integrate IP to the fundamental communication protocol standards work that these organizations performed.”

The Challenge of Verification

Sunrise’s Prithi Ramakrishnan is concerned about system verification.  “At a very high level, the main issue with IP is that the simulated environment is different from the final design environment.  Analog and RF IP is dependent on process/node, foundry, layout, extraction, model fidelity, and placement.  So you are either tied to just dropping it in ‘as is’ and treating it like a black box (nobody knows how it works and whether it meets the required specifications) or completely changing it (with the caveat that you can no longer expect the same results).  Digital IP needs to be resynthesized followed by placement and routing, and it takes several iterations to make the IP you got work the way you want it to work. In addition, this process is extremely tool-dependent.

Finally, there are system level issues like interoperability, interface and controls (how does the IP talk to the rest of the SoC). A very important, often overlooked factor is the communication between the IP providers and the SoC implementation houses – there are documents outlining integration guidelines, but without an automated process that takes in all that information, a lot could be lost in translation.”

The issue of how well a third party IP has been verified will always hunt designers unless the industry finds a way to make IP as trustworthy as the TI 7400 and equivalent parts of the early days.  Bernard Murphy, CTO at Atrenta observed: “One area that doesn’t get a lot of air-time is how a SoC verification team goes about debugging a problem around an IP. You have the old challenge – is this our bug or the IP developer’s bug? If the developer is down the hall, you can probably resolve the problem quickly. If they are now working for your biggest competitor, good luck with that. If this is a commercial IP, you work with an apps guy to circle around possibilities: maybe you are using it wrong, maybe you misunderstood the manual or the protocol, may be they didn’t test that particular configuration for that particular use-case… Then they bring in their expert and go back through the cycle until you converge on an answer. Problem is, all this burns a lot of time and you’re on a schedule. Is there a way to compress this debug cycle?”

He offers the following suggestion.  “One important class of things to check for is the above didn’t test that configuration for that use-case.  This is where synthesized assertions come in. These are derived automatically by the IP developer in the course of verifying the IP. They don’t look like traditional assertions (long, complex sequences of dependencies). They tend to be simpler, often non-obvious, and describe relationships not just at the boundary of the IP but also internal to the IP. Most importantly, they encode not just functionality but also the bounds of the use-cases in which the IP was tested. Think of it as a ‘signature’ for the function plus the verification of that function.”

Thomas L. Anderson, VP of Marketing at Breker Verification Systems pleads: integrate, but verify.  He argues that “The truth is that most SoC teams trust integration too much and verify too little. Many SoC products hit the market only after two or three iterations through the foundry. This costs a lot of money and risks losing market windows to competitors. Most SoC teams follow a five-step verification process:

  • Ensure that each block, whether locally designed or licensed as IP, is well verified
  • Use formal methods to verify that each block has been integrated into the SoC properly
  • Assemble a minimal chip-level simulation testbench and run a few sanity verification tests
  • Hand-write some simple C tests and run on the embedded processors in simulation or emulation
  • Run the production software on the processors in simulation, emulation, or prototyping
  • The problem with this process is that the tests in steps 3 and 4 are too simple since they are hand-written. They typically verify only one block at a time, ignoring interaction between blocks. They also perform only one operation at a time, so they don’t stress cache coherency or any inherent concurrency within the design. Humans aren’t good at thinking and coding in parallel. Thorough SoC pre-silicon verification can occur only with multi-threaded, multi-processor test cases that string blocks together into realistic scenarios representing end-user applications of the chip.”

    An Example of Complexity

    Charlie Cheng, CEO of Kilopass gave me an example of complexity in choosing the correct IP for a design by using sparse matrix math.

    With semiconductor IP comprising 90 percent of today’s semiconductor devices and memory IP accounting for over 50 percent of these complex SoCs, it’s no wonder that IP is the fastest growing sector of the overall semiconductor industry. As a result, managing third-party IP is a growing responsibility within today’s semiconductor companies. How to make the right choice from a growing quantity of IP is the major challenge facing engineering teams, purchasing departments, and executive management. The process of these groups buying IP can be viewed as a sparse matrix mathematical exercise but without the actual math formulas and data manipulation.


    The table shows two dimensions of a multi-dimensional matrix representing the variables confronting the purchasing company teams. In this two-dimensional matrix, imagine three additional tables for 1.8v operations with the four foundries at 28HPL, 28HPM, and 28HP.  Now, replicate this in a fourth dimension for the variable of 2.5v. Add a fifth and sixth dimension to the matrix for Vendor B’s OTP.  If this were a mathematical evaluation, a figure of merit would be assigned to each cell in each plane of the multidimensional matrix.

    For example, Vendor A’s OTP at 1.8v has JEDEC three-lot at 28HP at TSMC, UMC and GLOBALFOUNDRIES, similarly for 28HPM and 28HP but has only working silicon at 28LP.  Vendor B’s OTP may not have received three lot qualification at any of the vendors on any of the processes, but may have first silicon or one or two lot qualification on one or more of the vendors. In the mathematical exercise, a figure of merit would be assigned to the being fully qualified, one or two lot qualified, first silicon or not taped out.  Using matrix algebra, the formal mathematical exercise would return a result but an intuitive evaluation of the process would suggest vendor A with more three-lot qualifications at multiple foundries would have an edge over vendor B which did not.

    The above exercise would be typical of the evaluation occurring in the engineering team. A similar exercise would be occurring in the purchasing department with terms and conditions presented in the licensing agreement and royalty schedule each vendor submits. Corporate and legal would perform a similar exercise.

    If the mathematical exercise was actually performed and all the cells in the matrix had assigned values, then a definitive solution is easily achieved. However, if the cells throughout the matrix are sparsely populated, then the solution ends up with a probable outcome.

    Tags: Ansys, Apache, Atrenta, Breker, Cadence, Carbon Design, Dassault, IP integration, Kilopass, Mentor, Moore's Law, Semiconductor Process, Sonics, Sunrise, Synopsys, Uniquify, Verification

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